> For the complete documentation index, see [llms.txt](https://eeman.gitbook.io/twinbuilder-applications/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://eeman.gitbook.io/twinbuilder-applications/vhdl-ams/vhdlams-yu-fa.md).

# VHDL-AMS語法

## VHDL-AMS的基本語法

以下是一些VHDL-AMS的基本語法：

1. 實體(entity)和組件(component)的聲明

```
//
entity entity_name is
  port (
    input_port : in port_type;
    output_port : out port_type
  );
end entity_name;

component component_name is
  port (
    input_port : in port_type;
    output_port : out port_type
  );
end component_name;
```

2. 型別(type)的聲明

```
//
type type_name is range 0 to 10;  -- 宣告一個0到10的整數範圍型別
type type_name is array (0 to 9) of std_logic; -- 宣告一個std_logic數組型別
```

3. 變數(variable)的聲明

```
//
variable var_name : type_name := initial_value;
```

4. 輸入輸出(port)的聲明

```
//
entity entity_name is
  port (
    input_port : in port_type;
    output_port : out port_type
  );
end entity_name;
```

5. 運算符(operator)的使用

```
//
a := b and c; -- 邏輯與運算
a := b + c; -- 數值相加
```

6. 進程(process)的使用

```
// 
process (input_port)
begin
  if input_port = '1' then
    output_port <= '0';
  else
    output_port <= '1';
  end if;
end process;
```

7. 模擬環境(environment)的使用

```
// 
entity test is
end test;

architecture test_arch of test is
  component dut is
    port (
      input_port : in std_logic;
      output_port : out std_logic
    );
  end component;

  signal input_signal : std_logic := '0';
  signal output_signal : std_logic;

begin
  dut_inst : dut
    port map (
      input_port => input_signal,
      output_port => output_signal
    );

  input_process : process
  begin
    input_signal <= '0';
    wait for 10 ns;
    input_signal <= '1';
    wait for 10 ns;
    input_signal <= '0';
    wait for 10 ns;
    input_signal <= '1';
    wait;
  end process;
end test_arch;
```

8. 集合(collection)的聲明

```
// Some code
type type_name is array (0 to 9) of integer; -- 建立一個整數數組型別
variable array_var : type_name := (1, 2, 3, 4, 5, 6, 7, 8, 9, 10); -- 初始化一個整數數組變數
```

9. 函式(function)和程序(procedure)的聲明

```
// Some code
function function_name (arg1 : arg1_type; arg2 : arg2_type) return return_type is
  variable local_var : local_var_type;
begin
  -- 函式主體
end function;

procedure procedure_name (arg1 : arg1_type; arg2 : arg2_type) is
begin
  -- 程序主體
end procedure;
```

10. &#x20; 模擬時間控制

```
// Some code
wait for 10 ns; -- 等待10ns
wait until rising_edge(clk); -- 等待時鐘上升沿
```

11. &#x20;子程式(subprogram)的調用

```
// Some code
process (input_port)
begin
  output_port <= my_function(input_port);
end process;

function my_function (input : std_logic) return std_logic is
begin
  if input = '1' then
    return '0';
  else
    return '1';
  end if;
end my_function;
```

以上介紹的是VHDL-AMS的一些基本語法，請注意，VHDL-AMS並不是一個簡單的語言，對於新手來說可能需要花費一些時間學習和實踐。